The present invention relates generally to dielectrically isolated integrated circuits and more specifically to an improved dielectrically isolated integrated circuit formed by use of electrochemical etching.
Dielectrically isolated integrated circuits generally include a plurality of islands separated from a support on its side and bottom by a dielectric isolation. One of the earlier processes for forming these dielectric isolated islands included an anisotropically etching of a first surface of a substrate to form moats, covering the first surface and the moats with a dielectric isolation layer, followed by forming a support layer thereon. The structure is illustrated in FIG. 1 as having the original substrate 10 with dielectric isolation layer 12 and Support layer 14. A second surface 16 is mechanically removed down to a line 18 so as to expose the support layer 14 thereby forming dielectrically isolated islands. Devices are built in the surface along line 18. Since the second surface 16 is used as a reference plane for the grinding and polishing, any mismatch between surface 16 and the original surface 20 in which the moats are formed will result in the top surface 18 being non-parallel to the bottom surface 20. Since the original substrate 10 must be thick enough to be handled after etching without breaking and subsequently removed by grinding, control of the final thickness and parallelism of surfaces is reduced by grinding tolerances. Thus, the depth of the islands formed must be increased to increase the tolerance to compensate for any mismatching planarity. This unnecessarily increases the surface area of the islands and therefore adversely affects the density on the chip. Since the starting material 10 is also the regions which form the island, different starting resistivity materials must be used depending upon the circuit requirement.
Another method of forming dielectric isolation regions is electrochemical etching. This method is illustrated in FIG. 2 and includes epitaxially forming a second layer 22 on a first layer 24 wherein the first layer 24 has a lower resistivity than the second layer 22. The process is continued as in FIG. 1 wherein moats are anisotropically formed in the epitaxial layer 22 terminating within the second layer 22 followed by formation of a dielectric isolation layer 26 and a support layer 28. The composite structure is then placed in an etching bath and layer 24 is removed by electrochemical etching. This removes the layer 24 down to the interface 30 between the first and second layers 24 and 22. Layer 22 is then mechanically removed down to the dash line 32 exposing portions of the support layer 28 to form dielectrically isolated regions. Devices are formed in the surface 32. The electrochemical etch of FIG. 2 has been found to eliminate the errors produced by the mechanical removal of FIG. 1 since a majority of the material is removed by etching down to a substantially well defined surface 30 and then a small area between 30 and 32 is removed by mechanical means. In FIG. 1, the substantially thick layer 10 is reduced from surface 16 down to 18 by mechanical means. Also, since layer 22 is epitaxially grown, the parallel relationship between planes 30 and 34 of FIG. 2 is substantially greater than that between 16 and 20 of FIG. 1.
Electrochemical etching also has its problems. As noted in U.S. Pat. No. 3,536,600, a tapering effect can be produced and must be corrected. Similarly, because of the subsequent high temperature processing steps, impurities from layer 24 diffuse into layer 22 and consequently the interface layer 30 is not well defined. This induces additional errors in the removal of layer 24 to form a surface 30 which will be mechanically removed. The depth of the final resulting structure between planes 32 and 34 is increased by 10% to account for epitaxial growth errors. By increasing the depth, the lateral surface errors also increase and thereby reduces packing density. Thus, there exists the need for a method of forming dielectrically isolated islands wherein a final resulting surface is as parallel as possible to the bottom of the islands and therefore minimizing the depth error or tolerance which will substantially increase density.
An object of the present invention is to provide a method for fabricating dielectrically isolated regions of increased density.
Another object of the present invention is to provide a method of forming dielectrically isolated islands having increased depth accuracy.
Still another object of the present invention is to provide a method of fabricating dielectrically isolated regions which is capable of tailoring the resulting island resistivity and type while starting with a common substrate.
These and other objects of the present invention are attained by providing an indicator of a plane after electrochemical etching which is parallel to the plane of the surface in which the moats are etched. This allows electrochemical etching to be used with mechanical removal down to the final required depth resulting in substantial planarity of the top and bottom of the dielectrically isolated islands. The plane indicating moats are formed at the same time as the dielectric isolation moats which extend through the epitaxial layer and into the layer which is removed by electrochemical etching. By using an anisotropic etch, the depths of the two moats may be controlled within very close tolerances. The surface in which the moats are etched may be exposed to an introduction of impurities to form buried regions at the surface or to change the conductivity type or impurity concentration of the total resulting dielectrically isolated regions. The surface may also be etched and filled by epitaxial deposition of material of opposite conductivity type or increased impurity concentration.
Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.